Flip-chip semiconductor packaging technology is an advanced packaging technology, which primarily differs from conventional wire bonding packaging technology in that, a semiconductor chip to be packaged is mounted on a substrate in a face-down manner with a front surface of the semiconductor chip facing the substrate, and the semiconductor chip is electrically connected to the substrate by a plurality of bumps. As bonding wires occupying relatively more space are not needed for electrically connecting the semiconductor chip to the substrate in the flip-chip package structure, the entire package structure becomes lighter, thinner and smaller in profile.
Referring to FIG. 1, for bonding a bump 13 to a semiconductor chip 10, an under bump metallurgy (UBM) structure 12 is firstly formed on a bond pad 100 of the semiconductor chip 10. The UBM structure 12 comprises a metallic adhesive layer 12a forming on the bond pad 100, a barrier layer 12b for preventing diffusion, and a solder wettable layer 12c for connecting the bump 13. The UBM structure 12 provides functions such as bump connection, diffusion barrier, proper adhesion and so on between the bump 13 and the bond pad 100 of the semiconductor chip 10, such that a solder material can be applied to the UBM structure 12 and is then subjected to a reflow process to form the required bump 13.
The UBM structure usually comprises titanium-copper-nickel (Ti—Cu—Ni) metallic layers, and can be fabricated by for example sputtering, evaporation, plating and so on. The related prior arts to fabrication of the UBM structure include U.S. Pat. Nos. 5,137,845, 5,508,229, 5,773,359, etc.
A passivation layer 11 is applied on a surface of the semiconductor chip 10 having the bond pad 100 and is generally made of a polyimide material. Due to strong adhesion between the titanium metallic layer of the UBM structure 12 and the polyimide passivation layer 11, it usually occurs that during etching the metallic layers away from an area of the polyimide passivation layer 11 outside a predetermined bumping area, the titanium metallic layer cannot be completely removed from a surface of the polyimide passivation layer 11. As a result, residues of the titanium metallic layer are left on the passivation layer 11 of the semiconductor chip 10, and cause a problem of electrical leakage between bumping areas during chip operation after completing the flip-chip connection between the semiconductor chip and the substrate, thereby affecting electrical functions of the entire package.
FIG. 2 is a cross-sectional view showing electrically connecting the semiconductor chip 10 with the bump 13 to a substrate 20 by a flip-chip method. As described above, since the metallic adhesive layer (the titanium metallic layer) of the UBM structure 12 has strong adhesion with the polyimide passivation layer 11 and is difficult to be removed, not only the titanium metallic layer is formed at a position corresponding to the bond pad 100 of the semiconductor chip 10 but also residues 120 of the titanium metallic layer are left on the passivation layer 11 of the semiconductor chip 10. In such case, during a subsequent flip-chip underfilling process for filling an underfill material 21 between the semiconductor chip 10 and the substrate 20, delamination between the underfill material 21 and the semiconductor chip 10 and cracks of the bump 13 are caused, thereby adversely affecting the product reliability.
In response to the requirements of being light, thin and small in profile for various current electronic devices, there has been developed a packaging technology for directly electrically connecting a chip to an external device such as a printed circuit board and so on without using a chip carrier. For example, as to the wafer level chip scale packaging (WLCSP) technology, a redistribution layer (RDL) is formed on an active surface of a semiconductor wafer and redistributes electrical contacts of the wafer to proper positions, and then connection pads and UBM structures are formed on the proper positions to be electrically connected to the electrical contacts. Therefore, bumps can be implanted on the UBM structures, such that when the wafer is subsequently singulated to form single chips, the chips can be electrically connected to an external device such as a printed circuit board and so on by the bumps. However, if a bottom metallic layer of the UBM structure is a titanium metallic layer and a passivation layer applied on the chip is a polyimide layer, the foregoing problem of having residues of the titanium metallic layer is still caused.
Accordingly, the problem to be solved here is to provide a fabrication method of UBM structure, which can prevent residues of a bottom metallic layer of the UBM structure from being left on a passivation layer and thereby avoid unsatisfactory electrical functions and interface delamination.